1. Technical Field
The technology described in this patent application is generally directed to the field of phase detectors and clocking circuits that use such detectors. More specifically, a linear sample and hold phase detector is provided that is particularly useful in clock and data recovery (“CDR”) circuits as well as phase-locked loop (“PLL”) circuits. Novel CDR and PLL architectures are also described herein.
2. Description of the Related Art
Clock and data recovery circuits (CDRs) are typically used in data communications systems to extract and recover a clock from an input data stream. The recovered clock is then used to re-clock (or retime) the input data stream in order to provide an output data signal having reduced jitter.
Many communications standards require that the overall jitter generation of a given communication link is lower than some maximum value. These standards often require that the jitter generation is met in a frequency band that is both above and below the loop bandwidth of the CDR circuit. Meeting these requirements in systems that use stressful data patterns (i.e., CDR pathological patterns) that occur for long periods of time (i.e., within the CDR loop bandwidth) is difficult with conventional CDRs. Because the recovered clock signal is extracted from the input data signal, the phase of this recovered clock is susceptible to variation based on the input data jitter present and the bit pattern of the incoming data.
FIG. 1 is a block diagram of a prior art linear phase detector 100. This device includes a pair of D-type flip-flops 112, 114, and a pair of exclusive-OR gates 116, 118. The input data stream 102 is coupled to the data input of a first D-type flip-flop 112, and is also coupled to one input of a first exclusive-OR gate 116. The recovered clock signal 104, which is generated in another part of the circuit with which the phase detector 100 may be cooperating, is coupled to the clock inputs of the two flip-flops 112, 114. The phase of the recovered clock signal 104 is inverted at the clock input to the second D-type flip-flop 114. A retimed data signal 106 is output from the first D-type flip-flop 112 at its Q output. This same retimed data signal is also coupled to the other input of the first exclusive-OR gate 116 and to one input of the second exclusive-OR gate 118. The Q output of the second D-type flip-flop 114 (A1) is coupled to the other input of the second exclusive-OR gate 118.
Operationally, the two D-type flip-flops 112, 114 are cascaded to sample the incoming input data 102. The first flip-flop 112 samples the input data 102 on one recovered clock edge 104, and the second flip-flop 114 samples the retimed data signal 106 on the other recovered clock edge 104 (inverted). The input data 102 is compared with the retimed data signal 106 using the first exclusive-OR gate 116 to generate an UP pulse output 108. The retimed data signal 106 is compared with the delayed retimed data signal (at node A1) 120 using the second exclusive-OR gate 118 to generate a DN pulse output 110. The DN output pulse 110 width will remain one-half clock cycle wide. The UP output pulse 108 width will either increase or decrease in width depending on the phase difference between the input data signal 102 and the recovered clock signal 104. In the case of ideal phase alignment between these two signals 102/104, the UP output pulse 108 width will be the same as the DN pulse 110 width (i.e., one-half clock width).
FIG. 2A is a timing diagram 200 showing the operation of the prior art linear phase detector of FIG. 1 in which the recovered clock signal 104 is early with respect to the input data signal 102. Also shown in FIG. 2A are the retimed data 106, the node A1 signal 120, and the up and down pulse signals 108/110 from the pair of exclusive-OR gates 116, 118. As demonstrated in this figure, because the recovered clock signal 104 is early with respect to the input data signal 102—meaning that it crosses the zero line prior to the rising edge of the input data signal 102—then so too is the retimed data signal 106. As a result, the pulses generated at the UP output 108 shrink compared to the pulses generated at the DN output 110. In a typical CDR circuit using such a prior art phase detector, this will cause the recovered clock phase to be corrected by moving it late.
FIG. 2B is a timing diagram 250 showing the operation of the prior art linear phase detector of FIG. 1 in which the recovered clock signal 104 is late with respect to the input data signal 102. The same signals shown in FIG. 2A are also shown in FIG. 2B. As demonstrated in this figure, because the recovered clock signal 104 is late with respect to the input data signal 102—meaning that it crosses the zero line after the rising edge of the input data signal 102—then so too is the retimed data signal 106. As a result, the pulses generated at the UP output 108 widen in comparison to the pulses generated at the DN output 110. In a typical CDR circuit using such a prior art phase detector, this will cause the recovered clock phase to be corrected by moving it early.
FIG. 3 is a block diagram of a prior art clock and data recovery circuit 300 utilizing the linear phase detector 100 of FIG. 1. This circuit 300 includes, in addition to the linear phase detector 100, a charge pump circuit 302, a loop filter 304, and a voltage controlled oscillator 306 (“VCO”). The input data signal 102 is coupled to the linear phase detector and retiming circuit 100, which also receives the recovered clock signal 104 from the VCO 306 and generates the retimed data signal 106. As described above, the linear phase detector 100 produces UP and DN pulses 108/110 whose widths are representative of the relationship between input data edges and the recovered clock signal 104. These pulses are integrated and filtered by the charge pump 302 and loop filter 304. The filtered signal, in turn, drives a control port of the voltage controlled oscillator (VCO). The VCO output is the recovered clock signal 104 that feeds into the phase detector circuit 100.
The circuitry described above will typically tri-state (i.e., a high impedance output state that is neither a logic 1 or a logic 0) when there are no input data edges present at its input 102. Consequentially, the charge pump 302 and loop filter 304 will not charge up or down. During this time, any perturbations in the recovered clock signal 104 caused by, for example, supply noise, VCO phase noise, charge pump leakage, or other sources of perturbations, will not be immediately corrected by the CDR loop. This failure to respond when in tri-state mode adds to the overall jitter observed in the recovered clock signal 104, thus degrading the performance of the circuit against certain standards.
The prior art phase detector shown in FIG. 1 is also sensitive to input data transition density as well as component mismatches and non-ideal behavior. When data transition density decreases, so does the loop bandwidth in a CDR circuit such as shown in FIG. 3. This decrease in the loop bandwidth increases the CDR susceptibility to various noise sources or VCO frequency/phase drift. When long enough run lengths of certain input pattern types occur, this can cause the CDR to have different steady state recovered clock phases based upon the input data transition densities. This limitation of the prior art circuitry may further add to the overall jitter generation observed in the recovered clock signal 104.